FPGA-Based High-Speed Authenticated Encryption System -- A Smart Memory Accelerated Computed Tomography Parallel Backprojection -- Trinocular Stereo Vision Using a Multi Level Hierarchical Classification Structure -- Spatially-Varying Image Warping: Evaluations and VLSI Implementations -- An Ultra-Low-Power Application-Specific Processor with Sub-VT Memories for Compressed Sensing -- Configurable Low-Latency Interconnect for Multi-core Clusters -- A Hexagonal Processor and Interconnect Topology for Many-Core Architecture with Dense On-Chip Networks -- Fault-Tolerant Techniques to Manage Yield and Power Constraints in Network-on-Chip Interconnections -- On the Automatic Generation of Software-Based Self-Test Programs for Functional Test and Diagnosis of VLIW Processors -- SEU-Aware Low-Power Memories Using a Multiple Supply Voltage Array Architecture -- CMOS Implementation of Threshold Gates with Hysteresis -- Simulation and Experimental Characterization of a Unified Memory Device with Two Floating-Gates.