1 Introduction -- 1.1 Design of ASICs for high-throughput RSP -- 1.2 Overview and contributions of the book -- 2 Applications and Architecture -- 2.1 Characteristics of the application domain -- 2.2 The architectural style -- 2.3 Summary -- 3 The Underlying Synthesis Data Models -- 3.1 Operations and building blocks -- 3.2 Signal flow graph related issues -- 3.3 Summary -- 4 Literature Study -- 4.1 Traditional synthesis -- 4.2 Synthesis with accelerator data paths -- 4.3 Conclusions -- 5 The HLDM Script -- 5.1 The Cathedral-3 script -- 5.2 A script based approach -- 5.3 Initial flow graph transformations -- 5.4 ASU synthesis tasks -- 5.5 Motivation for the script -- 5.6 Synthesis of homogeneous architectures -- 5.7 Summary -- 6 Operation Clustering -- 6.1 Motivation -- 6.2 Related work -- 6.3 Operation clusters -- 6.4 Clustering techniques -- 6.5 Summary -- 7 Cluster to ASU Assignment -- 7.1 The cluster compatibility model -- 7.2 Solution techniques -- 7.3 Assignment in the presence of loops -- 7.4 Extensions -- 7.5 Summary -- 8 ASU Synthesis -- 8.1 The merging problem -- 8.2 Merging of a pair of structures -- 8.3 Extensions of pairwise merging -- 8.4 Ordering schemes for pairwise merging -- 8.5 N-way merging by iterative improvement -- 8.6 Summary -- 9 Demonstrator Designs -- 9.1 A 2 MHz ISDN modem -- 9.2 DCT/IDCT design for a videophone application -- 9.3 Address generation for a 2D motion estimator -- 9.4 Conclusions -- 10 Conclusions -- 10.1 Motivation of our approach -- 10.2 Contributions -- 10.3 Further work -- A Timing Analysis on Flow Graphs -- A.1 The model -- A.2 Timing vector algebra -- A.3 The critical path algorithm -- B The Constructive Clustering Algorithms -- B.1 Definitions -- B.2 Algorithms -- C Algorithms of the Assignment Chapter -- D Assignment Benchmarks -- D.1 The Silage code -- D.2 The results -- E Proof of Theorem 8.1. -- F ASU Synthesis Benchmarks -- F.1 Results for the pair-merging techniques -- F.2 Results for the ordering schemes -- F.3 Area correlation -- References.