Keynote Address -- Responsive Systems: A Marriage Between Real Time and Fault Tolerance -- Reconfiguration and Recovery -- Self-Diagnosis, Reconfiguration and Recovery in the Dynamical Reconfigurable Multiprocessor System DAMP -- Efficient Recovery of Statically Redundant Systems -- Implementations and Extensions of the Conversation Concept -- System Level Diagnosis -- Concurrent Error Detection Using Watchdog Processors in the Multiprocessor System MEMSY -- SEEDS: Simulation Environment for Dynamic Evaluation of Diagnostic Strategies -- An Expert System Shell for the Diagnosis of Parallel Computers -- Voting and Agreement -- Adaptive Fault Tolerance in Multi-Computer Systems Using Data Compaction and Two-Level Voting -- The Electoral District Strategy for Replicated Data in Distributed Systems -- Adaptive Byzantine Agreement in O(t) Phases -- Testing -- Scan Technology at Work -- Emulation of Scan Paths in Sequential Circuit Synthesis -- Testing of Fault-Tolerant Hardware -- Fault-Tolerant Circuits -- Coding Redundancy for Combinational Switching Circuits -- Optimal Error Detection Circuits for Sequential Circuits with Observable States -- Efficient Encoding/Decoding Circuitry for Systematic Unidirectional Error-Detecting Codes -- Array Testing -- Acceleration of RAM-Tests with Associative Pattern Recognition Methods -- Truth Table Verification for One-Dimensional CMOS ILA's -- Modelling -- On Modeling and Analysis of Latency Problem in Fault-Tolerant Systems -- Fixed Point Iteration in Availability Modeling -- Resource Allocation for Distributed Systems with Fault Tolerant Nodes -- Performability Evaluation of a Fault-Tolerant Multiprocessor Architecture Using Stochastic Petri Nets -- Applied Fault Tolerance -- Special Features of a Computer-Based German Reactor Protection System -- Fault-Tolerant Process Interface with Programmable Controllers -- A Simulation-Based Study of a Triple Modular Redundant System Using DEPEND -- Fault-Tolerant Arrays and Systems -- A Reconfigurable Instruction Systolic Array -- A New Approach for Designing Fault-Tolerant Array Processors -- A Performable BSM Architecture -- Interconnection Networks -- The Interlocking Bus Network for Fault-Tolerant Processor Arrays -- A Fault Tolerant Interconnection Network for Memory-Coupled Multiprocessor Systems -- Star Type Networks with Fault Tolerance -- Fault-Tolerant Software -- A Classification of Software Diversity Degrees Induced by an Analysis of Fault Types to Be Tolerated -- Optimal Design of Checks for Error Detection and Location in Fault Tolerant Multiprocessor Systems -- Testing Fault-Tolerant Protocols by Heuristic Fault Injection -- Appendix: Industrial Presentation -- A Practical Approach for a Fault-Tolerant Massively Parallel Computer -- List of Authors.