High-Speed Clock and Data Recovery -- Fundamental Stochastic Jitter Processes Associated with Clock and Data Recovery: A Tutorial -- Clock Recovery and Equalization Techniques for Lossy Channels in Multi Gb/s Serial Links -- Top-Down Bottom-Up Design Methodology for Fast and Reliable Serdes Developments in nm Technologies -- Mixed-Signal Implementation Strategies for High Performance Clock and Data Recovery Circuits -- Jointly Optimize Equalizer and CDR for Multi-Gigabit/s SerDes -- Time to Digital Conversion: An Alternative View on Synchronization -- High-Performance Amplifiers -- Dynamic Offset Cancellation in Operational Amplifiers and Instrumentation Amplifiers -- Current Sense Amplifiers with Extended Common Mode Voltage Range -- Low-Voltage Power-Efficient Amplifiers for Emerging Applications -- Integrated Amplifier Architectures for Efficient Coupling to the Nervous System -- Transimpedance Amplifiers for Extremely High Sensitivity Impedance Measurements on Nanodevices -- Design of High Power Class-D Audio Amplifiers -- Power Management -- Single-Inductor Multiple-Output Dc-Dc Converters -- Enhanced Ripple Regulators -- Robust DCDC Converter for Automotive Applications -- Highly Integrated Power Managemant Integrated Circuits in Advanced Cmos Process Technologies -- Wideband Efficient Amplifiers for On-Chip Adaptive Power Management Applications -- Design Methodology and Circuit Techniques for Any-Load Stable LDOs with Instant Load Regulation and Low Noise.