Wafer-Level Chip-Scale Packaging Analog and Power Semiconductor Applications

Başlık:

ISBN:

9781493915569

Personal Author:

Qu, Shichun. author.

Edition:

1st ed. 2015.

Yayın Bilgileri:

New York, NY : Springer New York : Imprint: Springer, 2015.

Fiziksel Tanımlama:

XVII, 322 p. 314 illus., 256 illus. in color. online resource.

Contents:

Chapter 1. Demand and Challenges for Wafer Level Analog and Power Packaging -- Chapter 2. Fan-In Analog Wafer Level Chip Scale Package -- Chapter 3. Fan-Out Analog Wafer Level Chip Scale Package -- Chapter 4. Wafer Level Analog Chip Scale Package Stackable Design -- Chapter 5. Wafer Level Discrete Power MOSFET Package Design -- Chapter 6. Wafer Level Packaging TSV/Stack die for Integration of Analog and Power Solution -- Chapter 7. Thermal Management, Design, Analysis for WLCSP -- Chapter 8. Electrical and Multi-Physics Simulations for Analog and Power WLCSP -- Chapter 9. WLCSP Typical Assembly Process -- Chapter 10. WLCSP Typical Reliability and Test.

Abstract:

This book presents a state-of-art and in-depth overview in analog and power WLCSP design, material characterization, reliability, and modeling. Recent advances in analog and power electronic WLCSP packaging are presented based on the development of analog technology and power device integration. The book covers in detail how advances in semiconductor content, analog and power advanced WLCSP design, assembly, materials, and reliability have co-enabled significant advances in fan-in and fan-out with redistributed layer (RDL) of analog and power device capability during recent years. Along with new analog and power WLCSP development, the role of modeling is a key to assure successful package design. An overview of the analog and power WLCSP modeling and typical thermal, electrical, and stress modeling methodologies is also provided. This book also: · Covers the development of wafer-level power discrete packaging with regular wafer-level design concepts and directly bumping technology · Introduces the development of the analog and power SIP/3D/TSV/stack die packaging technology · Presents the wafer-level analog IC packaging design through fan-in and fan-out with RDLs.

Subject Term:

Electronics and Microelectronics, Instrumentation.

Electronic Circuits and Systems.

Engineering Thermodynamics, Heat and Mass Transfer.

Added Author:

Liu, Yong.