Keynotes -- Life on the Treadmill -- Key Microarchitectural Innovations for Future Microprocessors -- The Challenges of Multicore: Information and Mis-Information -- Compilation Technologies -- Extracting Coarse-Grained Pipelined Parallelism Out of Sequential Applications for Parallel Processor Arrays -- Parallelization Approaches for Hardware Accelerators - Loop Unrolling Versus Loop Partitioning -- Evaluating Sampling Based Hotspot Detection -- Reconfigurable Hardware and Applications -- A Reconfigurable Bloom Filter Architecture for BLASTN -- SoCWire: A Robust and Fault Tolerant Network-on-Chip Approach for a Dynamic Reconfigurable System-on-Chip in FPGAs -- A Light-Weight Approach to Dynamical Runtime Linking Supporting Heterogenous, Parallel, and Reconfigurable Architectures -- Ultra-Fast Downloading of Partial Bitstreams through Ethernet -- Massive Parallel Architectures -- SCOPE - Sensor Mote Configuration and Operation Enhancement -- Generated Horizontal and Vertical Data Parallel GCA Machines for the N-Body Force Calculation -- Hybrid Resource Discovery Mechanism in Ad Hoc Grid Using Structured Overlay -- Organic Computing -- Marketplace-Oriented Behavior in Semantic Multi-Criteria Decision Making Autonomous Systems -- Self-organized Parallel Cooperation for Solving Optimization Problems -- Memory Architectures -- Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture -- An Enhanced DMA Controller in SIMD Processors for Video Applications -- Cache Controller Design on Ultra Low Leakage Embedded Processors -- Energy Awareness -- Autonomous DVFS on Supply Islands for Energy-Constrained NoC Communication -- Energy Management System as an Embedded Service: Saving Energy Consumption of ICT -- Java Processing -- A Garbage Collection Technique for Embedded Multithreaded Multicore Processors -- Empirical Performance Models for Java Workloads -- Chip-Level Multiprocessing -- Performance Matching of Hardware Acceleration Engines for Heterogeneous MPSoC Using Modular Performance Analysis -- Evaluating CMPs and Their Memory Architecture.