Opening -- The First Quartz Electronic Watch -- Arithmetics -- An Improved Power Macro-Model for Arithmetic Datapath Components -- Performance Comparison of VLSI Adders Using Logical Effort -- MDSP: A High-Performance Low-Power DSP Architecture -- Low-Level Modeling and Characterization -- Impact of Technology in Power-Grid-Induced Noise -- Exploiting Metal Layer Characteristics for Low-Power Routing -- Crosstalk Measurement Technique for CMOS ICs -- Instrumentation Set-up for Instruction Level Power Modeling -- Asynchronous and Adiabatic Techniques -- Low-Power Asynchronous A/D Conversion -- Optimal Two-Level Delay - Insensitive Implementation of Logic Functions -- Resonant Multistage Charging of Dominant Capacitances -- A New Methodology to Design Low-Power Asynchronous Circuits -- Designing Carry Look-Ahead Adders with an Adiabatic Logic Standard-Cell Library -- CAD Tools and Algorithms -- Clocking and Clocked Storage Elements in Multi-GHz Environment -- Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment -- Transistor Level Synthesis Dedicated to Fast I.P. Prototyping -- Robust SAT-Based Search Algorithm for Leakage Power Reduction -- Timing -- PA-ZSA (Power-Aware Zero-Slack Algorithm): A Graph-Based Timing Analysis for Ultra-Low Power CMOS VLSI -- A New Methodology for Efficient Synchronization of RNS-Based VLSI Systems -- Clock Distribution Network Optimization under Self-Heating and Timing Constraints -- A Technique to Generate CMOS VLSI Flip-Flops Based on Differential Latches -- Gate-Level Modeling -- A Compact Charge-Based Propagation Delay Model for Submicronic CMOS Buffers -- Output Waveform Evaluation of Basic Pass Transistor Structure -- An Approach to Energy Consumption Modeling in RC Ladder Circuits -- Structure Independent Representation of Output Transition Time for CMOS Library -- Memory Optimization -- A Low Energy Clustered Instruction Memory Hierarchy for Long Instruction Word Processors -- Design and Realization of a Low Power Register File Using Energy Model -- Register File Energy Reduction by Operand Data Reuse -- Energy-Efficient Design of the Reorder Buffer -- High-Level Modeling and Design -- Trends in Ultralow-Voltage RAM Technology -- Offine Data Profiling Techniques to Enhance Memory Compression in Embedded Systems -- Performance and Power Comparative Study of Discrete Wavelet Transform on Programmable Processors -- Power Consumption Estimation of a C Program for Data-Intensive Applications -- Communications Modeling and Activity Reduction -- A Low Overhead Auto-Optimizing Bus Encoding Scheme for Low Power Data Transmission -- Measurement of the Switching Activity of CMOS Digital Circuits at the Gate Level -- Low-Power FSMs in FPGA: Encoding Alternatives -- Synthetic Generation of Events for Address-Event-Representation Communications -- Posters -- Reducing Energy Consumption via Low-Cost Value Prediction -- Dynamic Voltage Scheduling for Real Time Asynchronous Systems -- Efficient and Fast Current Curve Estimation of CMOS Digital Circuits at the Logic Level -- Power Efficient Vector Quantization Design Using Pixel Truncation -- Minimizing Spurious Switching Activities in CMOS Circuits -- Modeling Propagation Delay of MUX, XOR, and D-Latch Source-Coupled Logic Gates -- Operating Region Modelling and Timing Analysis of CMOS Gates Driving Transmission Lines -- Selective Clock-Gating for Low Power/Low Noise Synchronous Counters -- Probabilistic Power Estimation for Digital Signal Processing Architectures -- Modeling of Propagation Delay of a First Order Circuit with a Ramp Input -- Characterization of Normal Propagation Delay for Delay Degradation Model (DDM) -- Automated Design Methodology for CMOS Analog Circuit Blocks in Complex Systems.